cache aliasing on hardware with virtually indexed caches

["John Newlin" <jnewlin@xxxxxxxxx>]

Hello,

Can someone point me to information regarding how the BSD kernel deals
with architectures that have cache aliasing issues?  E.G. sparc64, sh-4,
some of the mips implementations all have virtually indexed/physically
tagged
caches that are larger than the page size.  I'm just not sure where to
start looking.

Thanks,

-John



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